# Understanding Bit Depth Levels for Analog to Digital Conversion

I am a bit confused on bit depth regarding analog to digital conversion...

During the ADC process, I understand that bit depth essentially represents a number of levels that sample points can be mapped to (ie 16bit has 2^16 possible levels for samples to snap (quantize) to and 24 bit has 2^24 possible levels).

What I am confused about is how these bit depth levels are spread out over the y axis for a given analog waveform graph during the analog to digital conversion process.

For example, if I have some circuitry that can create an analog waveform with maximum and minimum values between -5V and +5V, and a resulting waveform is passed to an ADC to undergo the conversion process, are the bit depth levels spread out evenly to span this complete theoretical 10V range, or are they only spread out across the actual highest and lowest voltage points for that very specific standalone waveform?

Furthermore, why is it not problematic if ADCs are converting analog signals with different ranges (given the same bit depth), wouldn't the digital output at that point be representing different things for different signals (ie level 1 (bit 1) might represent 0.001V for one converted signal whereas level 1 might represent 0.002V for a different converted signal with a smaller voltage range). Wouldn't this lead to all kinds of consistency problems in the digital realm?